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| TSS902E Viterbi and Reed-Solomon FEC Decoder 1. Description Digital communication channels are inherently noisy, making transmission error control essential for reliable communication at low transmit power. The TSS902E is a single-chip Forward Error Correction decoder; it conforms to the MPEG-II transport layer protocol specified by ISO/IEC standard and FEC requirements of Digital Video Broadcasting (DVB) specification; its typical applications are DVB satellites, regenerative multi-media transmission satellites and military communications. The TSS902E capabilities rely on Viterbi and Reed-Solomon decoding algorithms to achieve extremely low bit-error rate (BER) on the transmitted data. Allowing discontinuous data blocks transmission, the TSS902E burst mode feature is unique. The component is made of the following blocks: G The inner decoder which performs the first level error detection and correction. This unit is made of a depuncturing block, a Viterbi decoder (k=7) and a synchronization/clock controller. G The convolutional deinterleaver, l=12 bytes for RS (204, 188, T=8) configuration. G The outer decoder performs the second level error protection, using a Reed Solomon (255, 239) error correcting process. G The descrambler for energy dispersal removal. G A micro-processor interface to setup the device and monitor the testability functions. While monitoring the inner Viterbi decoder BER output, the phase and the depuncturing pattern are tuned until the Viterbi decoder proper alignment is found. The Viterbi decoder output feeds the deinterleaver and Reed-Solomon decoder synchronization module. Once the synchronization words have been found, the deinterleaver, the outer Reed-Solomon decoder and the descrambler are properly aligned. Each functional block may be by-passed, giving more flexibility to a system designer. 2. Features 2.1. General G G G G G G G G G G Compliant with ETS 300 421 for DVB, DVB-S. Compliant with ISO/IEC-CD 13818-1 MPEG-II transport layer protocol. Input code rate frequency up to 10 MBits/sec at 5V. On-chip Bit Error Rate monitoring. SEU immunity better than 30 MeV/mg/cm2 Total dose better than 50 Krad (Si). Supply voltage 3 to 5V. Power consumption 1W at 5V / 10MHz external clock frequency (code rate 7/8). 0.6 m drawn CMOS, 3 metal layers. 132-pin MQFP. 2.2. Viterbi Decoder G Selectable code rates 1/2, 2/3, 3/4, 5/6 and 7/8 or automatic acquisition mode. Rev. D - April 1999 1 TSS902E G Hard decision or 3-Bit soft-decision decoder inputs. G Constraint length k = 7. G Eb/N0 for BER 2.10-4 (code rate 1/2) 3.5 dB. 2.3. Synchronization controller G Automatic synchronization capabilities for QPSK or BPSK. G Responds to inverted synchronization byte. G Programmable synchronization byte. 2.4. Convolutional deinterleaver G Error protected frame length n = 204. G Interleave depth I = 12. 2.5. Reed Solomon Decoder G Supported programmable shortened code length G Correction capability up to T = 8 bytes. K = 34 to 239, T = 8. 2.6. Descrambler (Energy Dispersal) G Polynomial generator q(x) = X15 + X14 + 1. G MPEG-II inverted synchronization byte. 2 Rev. D - April 1999 TSS902E 3. Term definitions Table 1: VITERBI TERM k NAME Encoding constraint length Traceback depth Puncturing Code rate DEFINITION Number of input bits contributing to the convolutional code. Length of path through the trellis over which the Viterbi decoder computes a decoded bit value likelihood. Transmission rate increasing process. Done by erasing some specific code bits before data transmission. Convolutional code input to output bits ratio. RANGE 7 2/3, 3/4, 5/6, 7/8 Table 2: CONVOLUTIONAL DEINTERLEAVER TERM I NAME Interleaving depth DEFINITION Interleaved stream separation. RANGE 12 Table 3: REED-SOLOMON TERM K R N T NAME Message length Check symbols Codeword length Error corrections DEFINITION Number of user data symbols in one message block. Symbols appended to the user data to detect errors. Sum of message and check symbols. N = K + R Maximum number of error corrections performed by the RS decoder. RANGE 34 p K p 239 bytes 16 bytes 50 p N p 255 bytes 8 Rev. D - April 1999 3 TSS902E 4. Functional description This section describes the TSS902E device architecture and its constituents functionality. DUP[7:0] AD[7:0] AS CS RDWRB RESETB TESTxxx MICROCONTROLLER INTERFACE & TEST IRQ REED SOLOMON DEC. VITERBI DECODER DEINTERLEAVER DEPUNCTURING DESCRAMBLER IEXT[2:0] CKOCTOUT DATAOUT[7:0] FRAMEOUT SYNCOUT CKBITOUT QEXT[2:0] BURSTSYNCIN CKBITEXT SYNCHRO. CONTROL PLL Serial DATAOUTS BURSTSYNCOUT XXXOUTF to external filter Figure 1: TSS902E block diagram 4.1. Synchronization The Synchronization Control block is made of two parts called Synchro-Bit and Synchro-Frame which algorithms are described hereafter. 4.1.1. The Synchro-Bit module The Synchro-Bit module performs the Depuncturing block and the Viterbi decoder synchronization by monitoring the Bit Error Rate (BER). The Viterbi BER calculation is done by the device during the averaging period whereas the monitoring period can be defined by the user in order to perform off-line statistical BER calculations. The Depuncturing module adds missing bits according to the code rate. Since the code rate may be unknown, the Depuncturing block may initially use a bad rate if the automatic mode has been selected (see RxVitControl register - A/M and FRE bits). Furthermore, the Depuncturing process may be uncorrectly synchronized although using the right code rate. Both conditions will lead to an unsatisfactory BER value. The Viterbi BER value is considered to be acceptable when it remains under the RxVitThreshold register value. This register is actually made of several registers, each associated to one code rate value (1/2, 2/3, 3/4, 5/6 and 7/8). If throughout the averaging period the BER value stays below the threshold, the Synchro-Bit block sets the SBF (Synchro Bit Found) flag within the RxVitStatus register, locks the PLL and allows the Synchro-Frame module to start the synchro word search. If, on the other hand, in automatic mode, the Viterbi decoder BER value exceeds its programmed threshold during the averaging period, the device will enter in sync-bit search mode trying to resolve at first the input data phase ambiguity within the current code rate; if the BER value still is too high, the device will assume that the depuncturing process 4 Rev. D - April 1999 TSS902E was not performed on the right input bits (the bits assumed to be missing were not on the right position) and the depuncturing state-machine will enter next state; finally, if the BER value still remains unacceptable, the code rate value will be changed and the device will restart the overall search process. Warning : if the programmed threshold value is too high, the bit synchronization may be found on a wrong position. In automatic mode, all the threshold registers must be properly programmed according to the expected noise and code rate. In semi-automatic mode, the user can just define the right value in the known code rate threshold register. In manual mode, the maximum threshold value can be programmed in the code rate threshold register; the use of FRE bit allows to find the bit synchronization for this code rate. (cf RxVitControl register usage) A loss of synchronization restarts a search of frame synchro. The Data processing of blocks placed after sync-frame block is restarted as well. The Synchro-Bit module can be bypassed by bit SYBE of the RxRSVitAct register. When set, the SYBE bit enables the synchronization between De-Puncturing and Viterbi blocks; when cleared, the Synchro-Bit module still maintains the SBF generation in order to allow other blocks to work; in this case the De-Puncturing rate is fixed (Rate = 1/2, no phase ambiguity). 4.1.2. The Synchro-Frame module Starting on successful Synchro-Bit process completion, the Synchro_Frame process waits for the frame synchronization word (47h) or the transport packet one (B8h) by default. The sync words search duration is limited by a timeout value defined through the RxSyncWCtl register TOV bits and RxVitSyncCompWord register SCW bits. An unsuccessful sync words search produces an interrupt and sets the RxVitRSInt0 register TiO flag. Whenever either sync word or bitwise inverted sync word is found, a counter is incremented and compared to the number of consecutive sync words at the expected position required to get synchronized (RxSyncWCtl register SY2/SY1/SY0 bits). The Synchro-Frame process remains in the sync word waiting loop until the expected number of consecutive sync words is reached, then the Synchro-Frame block sets the RxVitStatus register LCK bit (Synchro-Frame locked). The default sync word value is 47h but it may be changed to any value through the RxSyncWord register. The sync condition may take into account the bitwise inverted sync word search or not (RxVitSyncCompWord register CENA bit). The bitwise inverted sync word occurs every 8 frames by default but this value may be changed from 1 to 15 (RxVitSyncCompWord register SCW3 to SCW0 bits). A maximum number of allowed mismatching bits can be defined when expecting the sync word (RxSyncWctl register MSY bits). The Synchro-Frame process may restart under the following external conditions: D a general reset is applied to the device. D the Synchro_Frame module receives a restart signal from the Synchro-Bit block. D the bit synchronization is lost. D the Reed-Solomon decoder is out of sync (RxDeSyncWCtl register DRSM bit); this condition may be masked. D the descrambler module is out of sync (RxDeSyncWCtl register DSCM bit); this condition may be masked. The Synchro-Frame module will lose sync again after lock, when the sync word is not found at the expected position for a number of consecutive frames which is specified in RxVitDeSyncWCtl register DSY[2:0]. The maximum number of mismatching bits for a missed sync word is programmable (RxVitDeSyncWCtl register MDS[1:0] bits). A loss of synchronization restarts a search of frame synchro. The Data processing of blocks placed after sync-frame block is restarted as well. The Synchro-Frame module can be bypassed by bit SYE of the RxRSVitAct register. Rev. D - April 1999 5 TSS902E 4.2. Depuncturing The puncturing process is a way to change the code rate. Within a certain interval of code bits, some specific bits are simply not transmitted, i.e. erased. The De-Puncturing block must add these erased bits according to the transmission rate. This rate can be programmed in the RxVitRate register or automatically looked for by the Synchro_bit module. The ETS 300 421 (Digital brodcasting systems for television, sound and data services; Framing structure, channel cading and modulation for 11/12 GHz satellite services) defines punctured codes as in Table 1. Table 4: Punctured code definition Original Coding K G1 (X) G2 (Y) Code rates 1/2 P X:1 Y:1 dfree X:10 Y:11 2/3 P dfree 3/4 P X:101 Y:110 dfree 5/6 P X:10101 Y:11010 dfree 7/8 P X:1000101 Y:1111010 dfree 10 7 171oct 133oct I=X1 Q=Y1 I=X1Y2Y3 Q=Y1X3Y4 6 I=X1Y2 Q=Y1X3 5 I=X1Y2Y4 Q=Y1X3X5 4 I=X1Y2Y4Y6 Q=Y1Y3X5Y7 3 DePunctured Add Bit No Bit Note 1 = transmitted bit 0 = no transmitted bit For example, running with the 7/8 rate, the IEXT and QEXT inputs receive the following sequence: IEXT = a1, b2, b4, b6 QEXT = b1, b3, a5, a7 X2X4 X2Y3 X2Y3X4Y5 X2X3X4Y5X6Y7 At a coding rate of 7/8, the device has to generate 6 bitsat the proper position when it reads 8 bits in order to obtain 14 bits (i.e. 7 symbols). Depuncturing the above sequence gives: IEXT = a1, 1, 1, 1, a5, 1, a7 QEXT = b1, b2, b3, b4, 1, b6, 1 If the code rate is known, the Viterbi decoder module may be set to work in manual mode (see the RxVitControl register, A/M and FRE bits); in that case, the code rate must be defined through the RxVitRate register. If the code rate is unknown, the Synchro-Bit module can retrieve it by cycling through the 1/2, 2/3, 3/4, 5/6 and 7/8 code rates, looking for a valid pattern; the Synchro-Bit module may also consider a possible phase ambiguity or a depuncturing process error (the bits assumed to be missing were not at the right position). The depuncturing block can work in BPSK or QPSK modes (I and Q information being serial on IEXT input in BPSK mode, therefore the internal bit clock frequency is half the external one). The depuncturing module can be bypassed by bit DPE of the RxRSVitAct register. 6 Rev. D - April 1999 TSS902E 4.3. Viterbi decoder The Viterbi decoder reads data from the depuncturing module I and Q outputs and produces decoded bit information. The Viterbi block I[2:0] and Q[2:0] inputs may be configured to work in soft-decision or hard-decision mode by programming the RxVitControl register H/S bit. In soft-decision mode, the 3-bit input words are compared to seven thresholds. In hard-decision mode, only the IEXT and QEXT most significant bits are used; other bits are ignored. The Viterbi decoder can be bypassed by the RxRSVitAct register VE bit. The Viterbi decoder latency is 290 Ckbitrate clock periods. Ckbitrate is internally generated; its period is: Text T+ 2 Rate Where Text is the CKBITEXT clock period. For instance, if Text value is 100ns and Rate is 3/4, T value is 67ns. Latency = 19.5us The Viterbi module can be bypassed by bit VE of the RxRSVitAct register. 4.4. De-interleaver This part describes the process of convolutional de-interleaver as it is defined into ETS 300 421 . This device allows the error burst at the output of the inner decoder to be randomized on a byte basis in order to improve the burst error correction capability of the outer decoder (Reed-Solomon). The principle of the interleaver is the following one : the interleaver is composed of I = 12 branches, cyclically connected to the input byte-stream by the input switch. Each branch is a First-In, Fist-Out (FIFO) shift register, with depth M*j cells (where M = 17 = N/I, N = 204 = error protected frame length, I = 12 = interleaving depth, j = branch index). For synchronization purpose, the sync bytes (47h) and the inverted sync bytes (B8h) will always be routed in the branch "0" of the interleaver (corresponding to a null delay) The de-interleaver process is similar except that the branch indexes are inverted (i.e. j = 0 corresponds to the largest delay). The de-interleaver synchronization can be carried out by routing the first recognized sync byte in the "0" branch. The de-interleaver can be bypassed by bit DIE of the RxRSVitAct register. 4.5. Reed-Solomon decoder The inner code has to be an 8-error-correcting Reed-Solomon code over GF(2.8) (Galois Field). The natural length of this code is 255 symbols and since it can correct up to 8 errors, the code has 16 check symbols. This RS8 code can be shortened by any number of symbols resulting in a code length N, 50 - April 1999 7 TSS902E 4.6. Descrambler The energy dispersal is defined into ETS 300 421. The polynomial for the Pseudo Random Binary Sequence (PRBS) generator is : 1 + X14 + X15 and the loading sequence is "100101010000000". A MPEG-2 frame is 188 bytes long and the first byte is called MPEG-2 sync byte (47h) (MSB first). A transport packet is a group of 8 packets (8 x 188) where the first MPEG-2 sync byte is bit-wise inverted 47h to B8h. The randomizer will start with the first bit (MSB) of the first byte following the inverted sync. If the inverted sync word is not found and in order to aid other synchronization functions during MPEG-2, the PRBS will continue but its output will be disabled, leaving the sync bytes unrandomized. It has to be noticed that the Synchronization byte is provived by the RxSyncWord register. It is thus configurable. This block is also in charge of setting the "transport_error_indicator". In case the Write Error Bit (WER) is set and non-correctable errors happen in Reed-Solomon decoder (FlagError is set), the MSB of the first byte following the sync byte is forced to "1" after descrambling. If WER is reset, data are not affected. When the CENA bit is set (RxSyncCompWord register), the descrambler works as just described. When it is reset, the PRBS generator is reloaded at each frame. The synchronization byte is not inverted in this case. If an error occured on the MPEG-2 sync (B8h), 8 frames would be lost. To avoid this trouble a proper "Mainframe" synchronization is created using the SCW value (Synchro Complement Word). As soon as one inverted sync is found, a counter is set using the SCW value written in RxSyncCompWord register (8 by default for MPEG-2). Then, it generates this synchronization. So, only one frame is actually lost instead of eight. The descrambler can be bypassed by bit EDE of the RxRSVitAct register. 4.7. The burst mode In order to indicate to the circuit that the received data is of Burst type, the user must set the RxVitControl register BURSTM bit. 4.7.1. De-Interleaving burst mode constraints A burst packet may keep characteristics such as puncturing, Viterbi and RS coding. The de-interleaving process of packets will be significant only if the packets are made of n frames of 204 bytes. Likewise, the de-interleaving process will correctly achieve only if the burst packets and the inter-burst (duration between 2 packets) are multiple of (I * 1) 2 I 17 bytes ( for I + 12 ) 4.7.2. De-puncturing burst mode constraints During a Burst Mode transmission, there are several possible operating modes for the depuncturing block: 4.7.3. Freewheel Mode On each cycle, the received data, whether it is valid data or not, is depunctured according to the rate. The Freewheel mode is activated by clearing the RxVitRate register PBFrz and PBRst bits. 4.7.4. Freeze Mode Whenever the circuit receives invalid data, the state-machine, which handles the insertion of bits according to the rate, stops depuncturing and restarts when incoming data become valid. The Freeze mode may be activated by setting the RxVitRate register PBFrz bit. 4.7.5. Restart Mode Whenever the circuit receives invalid data, the state-machine, stops depuncturing, goes to the first step, and restarts when incoming data become valid. The external data input is then supposed to be a a1/b1 pair. This mode requires an inter-burst period greater or equal to 15 clock cycles The Restart mode may be activated by setting the RxVitRate register PBRst bit. 8 Rev. D - April 1999 TSS902E 4.7.6. Viterbi decoding burst mode constraints Patent pending. 4.7.7. Synchro-Bit burst mode constraints The Synchro-bit block can also be used during Burst Mode operation. However the errors issued from the Viterbi decoder will be taken into account only when they are recognized as being part of valid data. Since the Synchro-Frame process will start only after the Synchro-Bit is locked, the synchronization packets must be long enough to remove any ambiguity. 4.7.8. Synchro-Frame burst mode constraints In addition to the frame synchronization process, the Synchro-Frame block organizes the Viterbi data output as bytes. When operating in Burst Mode, this serial to parallel conversion is the only useful operation, since the Reed-Solomon decoder uses the bytes and Synchro-Frame signal SYNCOUT to perform its decoding. The Synchro-Frame block constraint is to have packets being multiple of 8 bits and an inter-burst of at least 7 bits. The ambiguity removal at the synchro-frame level can be done by software. The synchro frame signal SYNCOUT delimits the first generated byte and is regenerated at the beginning of each new frame. The frame length is defined in the RxRsFrameL register, thus allowing to determine the beginning of each new frame. Rev. D - April 1999 9 TSS902E 4.8. Global synchronization Before starting data process the PLL must be locked. According to the input clock bit frequency, it can be necessary to program the RxVitFreqIn register. The received data are first processed by the de-puncturing block, no matter their value. Then, the depunctured data go to Viterbi decoder. Viterbi counts the errors found in this data stream. The Synchro-Bit block is in charge of collecting the error number over a programmable averaging period (RxVitSearch), and comparing it to a programmable threshold (RxVitThresholdxx) with respect to the puncturing rate used for the de-puncturing block. This rate is programmable (RxVitRate) in manual or semi-automatic mode, or searched automatically in automatic mode. If the error number is greater than the threshold, there is no synchronization, and Synchro-Bit goes one state ahead in its state machine. There are several states for each puncturing rate since Synchro-Bit is also in charge of resolving /2 phase shift ambiguities as well as the ambiguity whether the de-puncturing process starts in the right phase. An interrupt is generated at the end of the averaging period (SBTE) if the error number is greater than the threshold. When the synchro bit is found (interrupt SBF), which happens when the error number is lower than the threshold, the search for a synchronization word (either 47h or its complemented value B8h for DVBS standard) starts in the Synchro-Frame block. However, the frame synchronization may not happen on the first synchro word found, since 47h or B8h may simply be a useful data in the stream. RxSyncWctl register is used to program the number of consecutive synchro words encountered at the right place (every n bytes, where n is the frame length programmed in RxRsFrameL) needed to confirm and synchronize the decoder, allowing 0, 1 or 2 mismatching bits in the "confirming" words (RxSyncWCtl). In the same way, the desynchronization conditions can be programmed in RxDeSyncWCtl register: the number of consecutive non-synchro words found every n bytes to desynchronize the decoder, and the number of error bits allowed. Moreover, RxSyncWctl register also contains a programmable time out value representing the maximum duration of the synchro word research after Viterbi synchro bit is found. If so, an interrupt is generated: TiO. It has to be noticed that too many errors in Reed-Solomon decoder and in the descrambler can have the synchro frame desynchronize. These respective interrupts (RSSL and DDSC) may be masked in RxDeSyncWCtl register. The interrupt indicating a synchro frame lock is LCK. The one for a synchro frame loss is SYL. All interrupts can be read from registers RxVitRSInt0 and RxVitRSInt1. The de-interleaver block starts operating at reception of a synchro word coming from Synchro-Frame. The Reed-Solomon decoder is able to correct up to 8 bytes. If Reed-Solomon detects more than 8 error bytes, it does not correct the error frame and it raises an error flag (interrupt RSER). After a certain number of consecutive error frames (programmable in the RxRSDeSyncFN register), Reed-Solomon is said to be desynchronized (interrupt RSSL), and may ask the Synchro-Frame to start another synchronization search. Due to Reed-Solomon encoding, each transmitted frame contains 16 check symbols in addition to the useful data. The descrambler is in charge of separating the useful data from RS check symbols. The BurstSyncOut signal is used to indicate the valid data. Since the descrambler simulates the process of energy dispersal within transport packets, it looks for B8h synchro words to start operating. However, it outputs only 47h synchro words at the beginning of each frame. If it does not find a B8h synchro word at the expected place, it sets the interrupt DDSC to warn the Synchro Frame block that it is desynchronized. 10 Rev. D - April 1999 TSS902E 5. Register Mapping and Description 5.1. Register Mapping The following control and status registers purpose is to synchronize the Viterbi decoder onto the right phase and puncturing rate as well as to monitor and tune the data stream quality and parameters. Table 5: Address Mapping Address 0x01 0x02 to 0x06 0x07 0x08 / 0x09 0x0A / 0x0B 0x0C / 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x20 / 0x21 0x22 / 0x23 0x24 0x30 0x31 / 0x32 0x33 0x34 0x35 0x40 RxVitControl RxVitThreshold RxVitSearch RxVitMonitor RxVitError RxVitErrorSync RxVitRate RxVitFreqIn RxSyncWord RxSyncWCtl RxDeSyncWCtl RxSyncStat RxVitSyncCompWord RxVitRSInt RxVitRSMask RxVitStatus RxRSFrameL RxRSError RxRSUncorrect RxRSFrameNb RxRSDeSyncFN RxRSVitAct Name Viterbi control Viterbi threshold Viterbi averaging period Viterbi monitoring period Viterbi error rate Viterbi synchro error Depuncturing rate Viterbi input frequency Synchro word Synchro word control Out of sync word control Synchro / Out of sync status Synchro complemented word Interrupt status Interrupt mask Viterbi status Reed Solomon frame length Reed Solomon bit error count RS uncorrected frame count Reed Solomon max frame count Reed Solomon out of sync frame Viterbi & RS activity control Access R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R R/W R R/W R R/W R R R/W R/W R/W Reset Signal RESETB RESETB RESETB RESETB RESETB,, Restart & write to RxVitMonitor RESETB & Restart RESETB RESETB RESETB RESETB RESETB RESETB & Restart RESETB RESETB & Read RxVitRSInt RESETB RESETB & Restart RESETB RESETB & Restart RESETB & Read RxRSUncorrect RESETB RESETB RESETB Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x47 0x01 0x01 0x00 0x88 0x00 0xFF / 0x3F 0x00 0xCC 0x00 0x00 0x00 0x1F 0xFF Rev. D - April 1999 11 TSS902E 5.2. Register Description 5.2.1. Viterbi Control RxVitControl 7 BURSTM Register address = 0x01 - Reset Value = 0x00 6 A/M 5 FRE 4 RST 3 SEC 2 S/O 1 PSK 0 H/S H/S - Hard/Soft mode: 0 = Soft decision (3 bits detection); 1 = Hard decision using IEXT and QEXT MSB only. PSK - Modulation mode: 0 = QPSK (two inputs: IEXT and QEXT); 1 = BPSK (IEXT single input) SEC-S/O: 00 = Offset Sign magnitude ; 01 = Offset Binary 10 = Two's Complement 11 = unused RST - Software RESET: 0 = Inactive; 1 = Allows the device to restart the synchronization phase A/M & FRE - Automatic / Manual and Freeze flags: A/M = 0 & FRE = 0: Automatic mode. Successive enabled code rates are tried with all possible phases, until the system is locked and the block synchro is found; this is the default setup (reset mode). A/M = 0 & FRE = 1: The code rate is frozen; if no synchro is found, the phase is swept but not the code rate. A/M = 1: Manual mode. The system is forced to a code rate (that you have previously defined), ignoring the time-out register and the BER value. In this mode, each FRE-bit 0 to 1 transition increments the phase, allowing full control of the synchronization by an external microcontroller, keeping the tuning giving the lowest BER. BURSTM - Burst Mode: 0 = Inactive (default); 1 = Active. 12 Rev. D - April 1999 TSS902E 5.2.2. Viterbi Threshold RxVitThreshold12 RxVitThreshold23 RxVitThreshold34 RxVitThreshold56 RxVitThreshold78 7 RA7 RB7 RC7 RD7 RE7 RA[7:0] RB[7:0] RC[7:0] RD[7:0] RE[7:0] 6 RA6 RB6 RC6 RD6 RE6 5 RA5 RB5 RC5 RD5 RE5 Register address = 0x02 - Reset value = 0x00 Register address = 0x03 - Reset value = 0x00 Register address = 0x04 - Reset value = 0x00 Register address = 0x05 - Reset value = 0x00 Register address = 0x06 - Reset value = 0x00 4 RA4 RB4 RC4 RD4 RE4 3 RA3 RB3 RC3 RD3 RE3 2 RA2 RB2 RC2 RD2 RE2 1 RA1 RB1 RC1 RD1 RE1 0 RA0 RB0 RC0 RD0 RE0 RA [7:0], RB [7:0], RC [7:0], RD [7:0], RE [7:0] - Bit Error Rate Threshold: Within each register, bits 7 to 0 represent a BER threshold (the average number of errors occuring during an averaging period). The current BER is compared to this programmable threshold. If it is greater, another phase (or another rate) is tried until the proper rate is found (Viterbi is synchronized). Maximum threshold values: SN [5:0] = 1xxxxx SN [5:0] = 01xxxx SN [5:0] = 001xxx SN [5:0] = 0001xx SN [5:0] = 00001x => Threshold = RX[7:0] & "0000000". .128 -> 32640 => Threshold = RX[7:0] & "000000" . . . 64 -> 16320 => Threshold = RX[7:0] & "00000" . . . . 32 -> 8160 => Threshold = RX[7:0] & "0000" . . . . . 16 -> 4080 => Threshold = RX[7:0] & "000" . . . . . . . 8 -> 2040 SN [5:0] = 00000x => Threshold = RX[7:0] & "00" . . . . . . . . 4 -> 1020 Note: SN[5:0] word purpose is described in the RxVitSearch register paragraph. RX[7:0] & "00" means that two zeros are appended to the register value, giving for this example a minimum and a maximum threshold values of 4 (R[7:0] = 0x01) and 1020 (R[7:0] = 0xFF). RX[7:0] stands for RA[7:0] to RE[7:0]. Rev. D - April 1999 13 TSS902E 5.2.3. Viterbi Search RxVitSearch 7 0 Register address = 0x07 - Reset Value = 0x00 6 0 5 SN5 4 SN4 3 SN3 2 SN2 1 SN1 0 SN0 SN [5:0] - Averaging Period: The averaging period register defines the number of incoming bits used by the device to calculate the BER. 0x3F -> 64K bits required to calculate the BER 0x3E -> 63K bits required to calculate the BER ... ... 0x02 -> 3K bits required to calculate the BER 0x01 -> 2K bits required to calculate the BER 0x00 -> 1K bits required to calculate the BER 5.2.4. Viterbi Monitoring RxVitMonitor0 7 Nb7 Register address = 0x08 - Reset value = 0x00 6 Nb6 5 Nb5 4 Nb4 3 Nb3 2 Nb2 1 Nb1 0 Nb0 RxVitMonitor1 0 Register address = 0x09 - Reset value = 0x00 0 Nb13 Nb12 Nb11 Nb10 Nb9 Nb8 Nb [13:0] - Monitoring Period: The monitoring period register defines the number of incoming bits required for BER statistical calculation done by the user. This value is a multiple of 1Kbits. Writing into this register starts a new monitoring period. At the end of this period, an interrupt may be generated (if enabled by the RxVitRSMask1 register MEMP bit). 0x3FFF -> 16384K bits required to calculate the BER 0x3FFE -> 16383K bits required to calculate the BER ... ... 0x0002 -> 3K bits required to calculate the BER 0x0001 -> 2K bits required to calculate the BER 0x0000 -> 1K bits required to calculate the BER 14 Rev. D - April 1999 TSS902E 5.2.5. Viterbi Error Rate (Read Only) RxVitErrorMsb 7 ERV15 Register address = 0x0A - Reset value = 0x00 6 ERV14 5 ERV13 4 ERV12 3 ERV11 2 ERV10 1 ERV9 0 ERV8 RxVitErrorLsb ERV7 Register address = 0x0B - Reset value = 0x00 ERV6 ERV5 ERV4 ERV3 ERV2 ERV1 ERV0 ERV [15:0] - Number of Error Bits: This 16-bits counter gives the number of error bits found along a monitoring period. It may be used for an off-line BER calculation done by the user. Whenever a monitoring period completes, this counter is frozen; it is reset to zero when a monitoring period starts. 5.2.6. Viterbi Error Synchro (Read Only) RxVitErrorSync0 Register address = 0x0C - Reset value = 0x00 7 ERS7 6 ERS6 5 ERS5 4 ERS4 3 ERS3 2 ERS2 1 ERS1 0 ERS0 RxVitErrorSync1 Register address = 0x0D - Reset value = 0x00 0 0 ERS13 ERS12 ERS11 ERS10 ERS9 ERS8 ERS [13:0] - Number of Incoming Bits: This 14-bits counter gives the number of Kbits received during a monitoring period before the BER value reaches the BER threshold (leading to a synchronization loss). It may be used to locate the context in which the synchronization loss occurred. In conjunction with the RxVitError register, it may also be used to tune the BER threshold. 5.2.7. Code Rate RxVitRate 7 PBFrz Register address = 0x0E - Reset value = 0x00 6 PBRst 5 0 4 E4 3 E3 2 E2 1 E1 0 E0 E [4:0] - Enable code Rate: This field sets the Viterbi decoder code rate when working in manual mode or semi-automatic mode. 0x01 -> code rate = 1/2 0x02 -> code rate = 2/3 0x04 -> code rate = 3/4 0x08 -> code rate = 5/6 0x10 -> code rate = 7/8 Only one bit should be set to 1. Any other E[4:0] contents leads to a 1/2 code rate selection. Rev. D - April 1999 15 TSS902E PBRst : Burst mode depuncturing Restart bit: 0 = The incoming IEXT/QEXT data stream is continuously depunctured even if BURSTSYNCIN input pin is held to zero. 1 = Stops the depuncturing process whenever BURSTSYNCIN input pin is set to zero (no valid burst data) and restarts on a ai/bj pair supposed to be the a1/b1 one. See the burst mode functional description. PBFrz : Burst mode dePuncturing Freeze bit: 0 = The incoming IEXT/QEXT data stream is continuously depunctured even if BURSTSYNCIN input pin is held to zero. 1 = Stops the depuncturing process whenever BURSTSYNCIN input pin is set to zero (no valid burst data) and restarts where it stopped. See the burst mode functional description. 5.2.8. Viterbi Input Frequency RxVitFreqIn 7 VCOC Register address = 0x0F - Reset value = 0x00 6 FREQ6 5 FREQ5 4 FREQ4 3 FREQ3 2 FREQ2 1 FREQ1 0 FREQ0 FREQ [6:0] - PLL External DividerValue in BPSK mode: FREQ [6 : 0] + Int [ 33.15 ] * 1 FInBit FREQ [6:0] - PLL External DividerValue in QPSK mode: FREQ [6 : 0] + Int [ 16.57 ] * 1 FInBit FInBit : Input frequency on CKBITEXT input pin: 1 MHz | FInBit | 10 MHz In Automatic Mode the default value should be: VCOC = 0 VCOC - VCO Control: This bit determines the PLL VCO to be used 0 = VCO2 is selected (output frequency range: 40 MHz to 130 MHz) 1 = VCO1 is selected (output frequency range: 130 MHz to 230 MHz) 5.2.9. Synchro Word RxSyncWord 7 SYW7 Register address = 0x10 - Reset value = 0x47 6 SYW6 5 SYW5 4 SYW4 3 SYW3 2 SYW2 1 SYW1 0 SYW0 SYW [7:0] - Synchronization Word: This register sets the Synchronization Word recognized by the Viterbi module during synchro and lock phases. The Viterbi synchronization module looks for SYW [7:0] and its complemented value every SCWth block (see RxVitSyncCompWord register). 16 Rev. D - April 1999 TSS902E 5.2.10. Synchro Word Control RxSyncWCtl 7 TOV1 Register address = 0x11 - Reset value = 0x01 6 TOV0 5 0 4 MSY1 3 MSY0 2 SY2 1 SY1 0 SY0 SY [2:0] - Number of Consecutive Synchronization Words: SY [2:0] is the number of consecutive Synchronization Words to be found to synchronize the decoder. MSY [1:0] - Maximum Number of Mismatching Bits: MSY [1:0] is the maximum number of mismatching bits allowed to declare a match when comparing data stream to the expected Synchronization Word. (0, 1 or 2 mismatching bits maximum. If MSY = 11, the number of allowed mismatching bits is set to 0). TOV [1:0] - Time Out Value: The Time Out Value programs the maximum duration of the Synchronization Word search after Viterbi synchro bit is found. If no Synchronization Word is found within this duration, an interrupt is generated and the external system must change parameters like the BER Threshold or the MSY value. 11 = Time out (bit period) = 8 x SCW [3:0] (see RxVitSyncCompWord register for SCW[3:0] definition). 10 = Time out (bit period) = 4 x SCW [3:0] 01 = Time out (bit period) = 3 x SCW [3:0] 00 = Time out (bit period) = 2 x SCW [3:0] 5.2.11. Loss of sync Word Control RxDeSyncWCtl Register address = 0x12 - Reset value = 0x01 7 DRSM 6 DSCM 5 0 4 MDS1 3 MDS0 2 DSY2 1 DSY1 0 DSY0 DSY [2:0] - Number of consecutive lost synchronization words: DSY [2:0] is the number of consecutive not expected synchronization words required to go out of sync. MDS [1:0] - Maximum number of mismatching bits: MDS [1:0] is the maximum number of mismatching bits allowed to declare a match when comparing data stream to the expected synchronization word (0, 1 or 2 bits maximum. If MDS = 11 the number of mismatching bits is set to 0). DSCM - Descrambler out of sync mask: 0 = Descrambler out of sync unmasked; 1 = Descrambler out of sync masked DRSM - Reed-Solomon out of sync mask: 0 = Reed -Solomon out of sync unmasked; 1 = Reed -Solomon out of sync masked 5.2.12. Synchro / Out of sync Status (Read Only) RxSyncStat 7 DSW3 Register address = 0x13 - Reset value = 0x00 6 DSW2 5 DSW1 4 DSW0 3 DSV3 2 DSV2 1 DSV1 0 DSV0 DSV [3:0] - Number of out of sync bits: DSV [3:0] is a counter incremented each time the Viterbi looses sync after the first lock. DSW [3:0] - Number of out of sync words: DSW [3:0] is a counter incremented each time the Synchronization Word mechanism looses sync after the first lock. Rev. D - April 1999 17 TSS902E 5.2.13. Complemented SyncWord RxVitSyncCompWord Register address = 0x14 - Reset value = 0x88 7 CENA 6 SAPI 5 0 4 0 3 SCW3 2 SCW2 1 SCW1 0 SCW0 SCW [3:0] - Complemented Synchro Word Position: The Complemented Synchro Word periodically appears after SCW frames. SAPI - Correct Pi Ambiguity in Burst Mode: 0 = No correction; 1 = ambiguity correction enabled in burst mode CENA - Complemented Sync Word Reseach Enable: 0 = Complemented sync word search disabled; 1 = Complemented sync word search enabled. 5.2.14. Interrupt Status (Read Only) RxVitRSInt0 7 ODFC Register address = 0x20 - Reset value = 0x00 6 TiO 5 SBF 4 LCK 3 SYL 2 RSSL 1 RSER 0 TEBRS RxVitRSInt1 7 0 Register address = 0x21 - Reset value = 0x00 6 0 5 DDSC 4 ODBC 3 SBTE 2 EAP 1 MECO 0 EMP TEBRS - Reed-Solomon Monitoring Period Finished RSER - Reed-Solomon Found More Than 9 Bytes in Error RSSL - Reed-Solomon out of sync SYL - Synchro Lost LCK - Synchro Word Found SBF - Synchro Bit Found TiO - Time Out Period Without finding synchro word ODFC - Overflow out of sync Frame Counter EMP - Viterbi Monitoring Period Finished MECO - Monitoring Errors Counter Overflow EAP - Viterbi Averaging Period Finished SBTE- Synchro Bit Threshold Error ODBC - Synchro Bit Lost Counter Overflow DDSC - Descrambler out of sync The above bits give information about the interrupt generation event. A bit set to 1 shows the interrupt origin. 18 Rev. D - April 1999 TSS902E 5.2.15. Interrupt Mask RxVitRSMask0 7 MODFC Register address = 0x22 - Reset value = 0xFF 6 MTO 5 MPRF 4 MLCK 3 MSYL 2 MRSSL 1 MRSER 0 MTEBRS RxVitRSMask1 7 0 Register address = 0x23 - Reset value = 0x3F 6 0 5 MDDS 4 MODBC 3 MSBTE 2 MEAP 1 MMECO 0 MEMP MTEBRS - Reed-Solomon Monitoring Period Finished MRSER - Reed-Solomon Found More Than 9 Bytes in Error MRSSL - Reed-Solomon out of Sync MSYL - Synchro Lost MLCK - Synchro Word Found MPRF - Synchro Bit Found MTO - Time Out Period Without finding Synchro Word MODFC - Overflow out of sync Frame Counter MEMP - Viterbi Monitoring Period Finished MMECO - Monitoring Errors Counter Overflow MEAP - Viterbi Averaging Period Finished MSBTE - Synchro Bit Threshold Error MODBC - Synchro Bit Lost Counter Overflow MDDS - Descrambler out of sync When set to 1, the above bits mask the corresponding interrupts. 5.2.16. Viterbi Status (Read Only) RxVitStatus 7 PLU Register address = 0x24 - Reset value = 0x00 6 EMP 5 TiO 4 SBF 3 LCK 2 PR2 1 PR1 0 PR0 PR [2:0] - Current Code Rate : In automatic mode, PR [2:0] indicates the current code rate according to the following table: 100 = code rate 7/8 011 = code rate 5/6 010 = code rate 3/4 001 = code rate 2/3 000 = code rate 1/2 LCK - Synchro Word Found: 0 = Searching for Synchro Word; 1 = Synchro word found and locked. SBF - Synchro Bit Found: SBF indicates the code rate search status. This bit is irrelevant in manual mode. 0 = Searching for Synchro bit; 1 = Synchro bit found and locked. TiO - Time Out Period Without SWF: 0 = (see conditions for TiO = 1) 1 = When Synchro Bit is found and no Synchro Word is found within the Time Out duration. EMP - Viterbi End of Monitoring Period: Rev. D - April 1999 19 TSS902E 0 = Monitoring Period not finished. 1 = Monitoring Period finished. A write access to the RxVitMonitor registers resets this bit. PLU - PLL Lock/Unlock: 0 = Pll unlocked; 1 = Pll locked. 5.2.17. Reed Solomon Frame Length RxRSFrameL 7 FL7 Register address = 0x30 - Reset value = 0xCC 6 FL6 5 FL5 4 FL4 3 FL3 2 FL2 1 FL1 0 FL0 FL [7:0] - Frame Length: The Reed Solomon decoder is based on the original RS (255, 239, T = 8) code, and supports the following shortening K = 34 to 239. This also includes the DVB specification of RS (204, 188, T = 8). The default value is 204 (0xCC), and might be overwritten by values from 50 (34 + 16) to 255 (239 + 16). 5.2.18. Reed-Solomon Bit Error Count (Read Only) RxRSErrLsb 7 E7 Register address = 0x31 - Reset value = 0x00 6 E6 5 E5 4 E4 3 E3 2 E2 1 E1 0 E0 RxRSErrMsb 7 E15 Register address = 0x32 - Reset value = 0x00 6 E14 5 E13 4 E12 3 E11 2 E10 1 E9 0 E8 E [15:0] - RS Bit Error Count: E [15:0] stores the value of the RS bit error count used to calculate the Reed-Solomon BER. If there are more than 8 bytes on error in a frame, the bit error count is not incremented. If there are 8 bytes on error in a frame with 8 bits on error in each byte, the bit error count is not incremented; this is a bug that will be fixed in the next version. 5.2.19. Reed-Solomon Uncorrected Frames Count (Read Only) RxRSUncorrect 7 UNF7 6 Register address = 0x33 - Reset value = 0x00 5 UNF5 4 UNF4 3 UNF3 2 UNF2 1 UNF1 0 UNF0 UNF6 UNF [7:0] - UnCorrected Frame Number: UNF [7:0] is the RS Frame error counter used to calculate the Reed-Solomon BER. UNF error count is incremented each time there are more than 8 bytes on error in a frame. 20 Rev. D - April 1999 TSS902E 5.2.20. Reed Solomon Maximum Frame Count RxRSFrameNb 7 FN7 6 FN6 Register address = 0x34 - Reset value = 0x00 5 FN5 4 FN4 3 FN3 2 FN2 1 FN1 0 FN0 FN [7:0] - Maximum Frame Count: FN [7:0] bits are the 8-Msb preset value of a 10-bit counter used to define the RS monitoring period duration. At the end of this time, the RxRSErr and RxRSUncorrect registers are updated and an interrupt (TEBRS) is generated. Writing into this register starts a new RS monitoring period. 5.2.21. Reed-Solomon out of Sync Frame RxRSDeSyncFN 7 WER 6 0 Register address = 0x35 - Reset value = 0x1F 5 0 4 DRSY4 3 DRSY3 2 DRSY2 1 DRSY1 0 DRSY0 DRSY [4:0] - Reed-Solomon out of sync Frame Number: DRSY[4:0] is the number of consecutive Reed-Solomon erroneous frames required to indicate sync loss. WER - Write Error Bit: 0 = Data is not affected. 1 = If a non-correctable error occurs, the "transport_error_indicator" (Msb of the first byte following the synchro byte) is forced to '1' after descrambling. Rev. D - April 1999 21 TSS902E 5.2.22. Viterbi and Reed-Solomon Activity Control RxRSVitAct 7 SYBE 6 EDE Register address = 0x40 - Reset value = 0xFF 5 RSE 4 DIE 3 SYE 2 VE 1 DPE 0 PLLE PLLE - PLL Enable: 0 = PLL disabled, the clock rate equals external clock rate and the PLL input clock PLL is held low. 1 = PLL enabled, the clock rate is generated by the PLL. DPE - DePuncturing Enable: 0 = Data is not affected; 1 = Input data stream is depunctured. VE - Viterbi Enable: 0 = Data is not affected; 1 = Input data stream is corrected by the Viterbi decoder. SYE - Synchro Enable: 0 = Parallel data come from external pin (IEXT, QEXT, TESTIERA, TESTQERA). 1 = Serial flow is converted to parallel data by Synchro. DIE - De-Interleaver Enable: 0 = Data is not affected; 1 = Input data stream is deinterleaved. RSE - Reed-Solomon Enable: 0 = Data is not affected; 1 = Errors are corrected. EDE - Energy Dispersal removal Enable: 0 = Data is not affected; 1 = Output data from RS is descrambled. SYBE - Synchro Bit Enable: 0 = The Synchro bit found is generated to allow other blocks to work (except Viterbi decoder). 1 = The Viterbi error processing is enabled. 22 Rev. D - April 1999 TSS902E 6. Signals Descriptions and Specifications 6.1. Signals Descriptions Name Active State or Edge Low # edge Low / High Chip select input. Address latch input. Read (high) / Write (low) signal. Address bus. Bi-directional data bus. Low Low Reset. When active, forces all blocks into a known state. Must be used as specified in the AC parameters section. Interrupt output. May be used by the external system for sync monitoring purpose. Description MICROPROCESSOR SIGNALS CS AS RDWRB AD[7:0] DUP[7:0] RESETB IRQ DEMODULATOR SIGNALS IEXT[2:0] QEXT[2:0] BURSTSYNCIN PLL SIGNALS CKBITEXT XXXOUTF OUTPUT SIGNALS DATAOUT[7:0] CKOCTOUT SYNCOUT FRAMEOUT DATAOUTS CKBITOUT BURSTSYNCOUT TEST SIGNALS TESTIERA TESTQERA TESTCKOCT TESTCKOCT90 TESTSYNC TESTCKBIT TESTCKBIT90 # edge # edge High edge edge Depuncturing block I test input. Depuncturing block Q test input. Byte-format data test clock. Byte-format data test clock (Pi/2 delayed from TESTCKOCT). Indicates a sync word occurrence. In test mode, emulates the depunctured data clock. In test mode, emulates the depunctured data clock (Pi/2 delayed from TESTCKBIT). High # edge High High Data output bus. May be read on the CKOCTOUT output clock rising edge. Parallel data output sampling signal. Active whenever a frame sync word is found. Active whenever a multi-frame sync word is found. Serial data output. May be read on the CKBITOUT output clock rising edge. Serial data output sampling signal. Active whenever a multi-frame sync word is found; remains high for a frame length duration. edge Symbol clock for IEXT and QEXT. PLL external RC filter connection. High 3-bit soft decision input. Use IEXT[2] for hard decision input. 3-bit soft decision input. Use QEXT[2] for hard decision input. Burst mode control pin. When high, indicates an incoming data burst. When low, indicates irrelevant data on IEXT and QEXT pins in burst mode. Rev. D - April 1999 23 TSS902E Name Active State or Edge Description DEPUNCTURING SIGNALS IEXT[2:0] QEXT[2:0] BURSTSYNCIN CKBITEXT TESTCKBIT DATAOUT[7:5] DATAOUT[4:2] DATAOUT[1] DATAOUT[0] CKBITOUT VITERBI SIGNALS IEXT[2:0] QEXT[2:0] TESTIERA TESTQERA BURSTSYNCIN High High High 3-bit soft decision input (with or without added bits according to the usage of Depuncturing block). Use IEXT[2] for hard decision input. 3-bit soft decision input (with or without adding bits according to the usage of Depuncturing block). Use QEXT[2] for hard decision input. indicates the I adding bits if the depuncturing block is not used indicates the Q adding bits if the depuncturing block is not used If the depuncturing block is not used, the activity on this signal indicates an incoming data. otherwise it indicates irrelevant data on IEXT and QEXT pins. With the Depuncturing block this signal value makes sense only if the Burst mode is programmed. TESTCKBIT TESTCKBIT90 CKBITEXT DATAOUT[0] CKBITOUT edge edge edge Witout PLL, emulates the depunctured data clock. Witout PLL, emulates the depunctured data clock (Pi/2 delayed from TESTCKBIT) External clock bit needed if the depuncturing block is used. Its frequency depends on the usage of the depuncturing block. Viterbi serial output. Serial data output sampling signal. High edge edge 3-bit soft decision input. Use IEXT[2] for hard decision input. 3-bit soft decision input. Use QEXT[2] for hard decision input. Burst mode control pin. When high, indicates an incoming data burst. When low, indicates irrelevant data on IEXT and QEXT pins in burst mode. Symbol clock for IEXT and QEXT. In test mode without PLL, emulates the depunctured data clock. represent Iout[2:0] with added bits according to the code rate represent Qout[2:0] with added bits according to the code rate when this output equal 1, Iout are added bits (EraseI) when this output equal 1, Qout are added bits (EraseQ) Serial data output sampling signal. SYNCHRO_BIT SIGNALS (without VITERBI and DEPUNCTURING blocks) BURSTSYNCIN TESTSYNC TESTCKBIT CKBITEXT High High edge edge When high, indicates an incoming data. When high, emulates a Viterbi error. External clock bit needed if the Pll is not used External clock bit needed if the Pll is used SYNCHRO_FRAME SIGNALS (without VITERBI, DEPUNCTURING and SYNCHRO_BIT blocks) IEXT[2] TESTCKBIT CKBITEXT BURSTSYNCIN TESTSYNC DATAOUT[7:0] DATAOUTS SYNCOUT BURSTSYNCOUT High High edge edge High High Input serial data. External clock bit needed if the Pll is not used External clock bit needed if the Pll is used When high, indicates a valid incoming data in Burst mode. When high, indicates an incoming data in Burst mode. This signal must be set to one 6 bits before the real valid data and set to zero 6 bits before the burst end. Parallel Data output bus. May be read on the CKOCTOUT output clock rising edge. Serial data output. May be read on the CKBITOUT output clock rising edge. Active whenever a frame sync word is found or during the first frame word in burst mode according to the frame length. Active whenever a synchro-frame is locked or when DATAOUT is valid in burst mode. 24 Rev. D - April 1999 TSS902E Name CKOCTOUT CKBITOUT Active State or Edge Parallel data output sampling signal. Serial data output sampling signal. Description CONVOLUTIONAL DEINTERLEAVER SIGNALS IEXT[2:0] QEXT[2:0] TESTIERA TESTQERA CKBITEXT TESTCKBIT TESTCKOCT TESTSYNC DATAOUT[7:0] DATAOUTS SYNCOUT BURSTSYNCOUT CKOCTOUT CKBITOUT REED-SOLOMON DECODER SIGNALS IEXT[2:0] QEXT[2:0] TESTIERA TESTQERA CKBITEXT TESTCKBIT TESTCKOCT TESTCKOCT90 TESTSYNC BURSTSYNCIN DATAOUT[7:0] DATAOUTS SYNCOUT BURSTSYNCOUT CKOCTOUT CKBITOUT DESCRAMBLER SIGNALS IEXT[2:0] QEXT[2:0] TESTIERA TESTQERA Input Descrambler parallel data[7:5], IEXT[2] => Input Descrambler serial data if Synchro_Frame is used. Input Descrambler parallel data[4:2] Input Descrambler parallel data[1] Input Descrambler parallel data[0] edge edge edge edge High High Input Reed-Solomon parallel data[7:5], IEXT[2] => Input Reed-Solomon serial data if Synchro_Frame is used. Input Reed-Solomon parallel data[4:2] Input Reed-Solomon parallel data[1] Input Reed-Solomon parallel data[0] External clock bit needed if the Pll is used and Synchro_Frame is used. External clock bit needed if the Pll is not used and Synchro_Frame is used. External clock byte needed if Synchro_frame is not used External clock byte needed if Synchro_frame is not used (Pi/2 delayed from TESTCKOCT) Emulates the input frame sync word if Synchro_frame is not used according to the Frame lenght. When high, indicates a valid incoming Frame. Parallel Data output bus. May be read on the CKOCTOUT output clock rising edge. Serial data output. May be read on the CKBITOUT output clock rising edge only if an input clock bit is used. Active whenever a frame sync word is transmitted to the output When high, indicates a valid output Frame. Parallel data output sampling signal. Serial data output sampling signal. High High edge edge edge High Input DeInterleaver parallel data[7:5], IEXT[2] => Input DeInterleaver serial data if Synchro_Frame is used. Input DeInterleaver parallel data[4:2] Input DeInterleaver parallel data[1] Input DeInterleaver parallel data[0] External clock bit needed if the Pll is not used External clock bit needed if the Pll is used External clock byte needed if Synchro_frame is not used Emulates the input frame sync word if Synchro_frame is not used Parallel Data output bus. May be read on the CKOCTOUT output clock rising edge. Serial data output. May be read on the CKBITOUT output clock rising edge. Active whenever a frame sync word is transmitted to the output Active whenever a complete convolutional Interleaving sequence is processed and all output data are valid Parallel data output sampling signal. Serial data output sampling signal. Rev. D - April 1999 25 TSS902E Name CKBITEXT TESTCKBIT TESTCKOCT TESTSYNC DATAOUT[7:0] DATAOUTS SYNCOUT BURSTSYNCOUT FRAMEOUT CKOCTOUT CKBITOUT High High High Active State or Edge edge edge edge High Description External clock bit needed if the Pll is used and Synchro_Frame is used. External clock bit needed if the Pll is not used and Synchro_Frame is used. External clock byte needed if Synchro_frame is not used Emulates the input frame sync word if Synchro_frame is not used according to the Frame lenght. Parallel Data output bus. May be read on the CKOCTOUT output clock rising edge. Serial data output. May be read on the CKBITOUT output clock rising edge only if an input clock bit is used. Active whenever a frame sync word is transmitted to the output Active whenever a multi-frame sync word is found; remains high for a frame length duration without Reed-Solomon syndrome (Active during 188 byte) . Active whenever a multi-frame sync word is found. Parallel data output sampling signal. Serial data output sampling signal. 26 Rev. D - April 1999 TSS902E 6.2. Pinout Description Rev. D - April 1999 27 TSS902E 7. Programming and Operation Modes This chapter describes how to operate the TSS902E from the programmer's point of view. Most of the TSS902E registers are made of several fields. In the following descriptions, the concerned registers and fields names will be mentioned as well as recommended values. You should read the Register Description section anyway since some registers particularities like unvalid registers values are not covered in this chapter. 7.1. Device Activity Control In order to give great flexibility to a system designer, each functional block may be by-passed. You will probably start the TSS902E setup by enabling the blocks you want to be activated. The following sections show how to configure the device in order to activate some blocks only, or the whole circuit. 7.1.1. Using the Viterbi Decoder Only Working with the Viterbi decoder only requires three conditions: D The rate is 1/2; i.e. there is no data puncturing. D QPSK mode is used When running in BPSK mode, the I/Q data stream coming to the IEXT pins with the I1 - Q1 - I2 - Q2 - I3 - Q3 sequence is demultiplexed by the depuncturing block; consequently, using the BPSK mode requires the depuncturing block to be enabled. D For the Viterbi decoder to run alone properly, you must be able to provide it with two stable clock signals. If you can not guarantee the clocks stability, you must use the depuncturing block which compensates the clocks jitter. IEXT(2:0) DATAOUT(0) QEXT(1:0) VITERBI DECODER TESTCKBIT TESTCKBIT90 CKBITOUT IEXT/QEXT data is clocked on the TESTCKBIT rising edge; there is a Pi/2 phase delay between TESTCKBIT and TESTCKBIT90. The others device pins must be set as follows: D TESTIERA, TESTQERA and TESTSYNC connected to VSS (Ground). D CKBITEXT, TESTCKOCT and TESTCKOCT90 connected to VCC. RXRSVITACT register = 0X84 28 Rev. D - April 1999 TSS902E 7.1.2. Using the Viterbi Decoder And The Depuncturing Block - Without PLL IEXT(2:0) DATAOUT(0) QEXT(1:0) VITERBI DECODER CKBITEXT & DEPUNCTURING CKBITOUT TESTCKBIT TESTCKBIT90 The CKBITEXT clock is the IEXT and QEXT symbols clock. These signals timing relationship is shown in section 8.6. The TESTCKBIT clock frequency depends on the BPSK/QPSK mode and the puncturing rate as follows: D BPSK TESTCKBIT_freq = CKBITEXT_freq x Punct_Rate If Punct_Rate = 1/2, you must generate a TESTCKBIT clock with a frequency of half the CKBITEXT one. In BPSK mode, the data stream comes on IEXT(2:0) pins only; the QEXT(2:0) must be connected to ground. D QPSK TESTCKBIT_freq = CKBITEXT_freq x Punct_Rate x 2 If Punct_Rate = 1/2, TESTCKBIT_freq = CKBITEXT_freq The TESTCKBIT90 clock frequency is the same than the TESTCKBIT one; there is only a Pi/2 phase shift between them. The others device pins must be set as follows: D TESTIERA, TESTQERA and TESTSYNC connected to VSS (Ground). D TESTCKOCT and TESTCKOCT90 connected to VCC. RXRSVITACT register = 0X86 Rev. D - April 1999 29 TSS902E 7.1.3. Using the Viterbi Decoder And The Depuncturing Block - With PLL Using the TSS902E with its PLL is much more simple since you do not need to generate the TESTCKBIT and TESTCKBIT90 clocks. IEXT(2:0) QEXT(1:0) VITERBI DECODER & DEPUNCTURING & PLL CKBITOUT DATAOUT(0) CKBITEXT The CKBITEXT clock is the IEXT and QEXT symbols clock. These signals timing relationship is shown in section 8.6. The others device pins must be set as follows: D TESTIERA, TESTQERA and TESTSYNC connected to VSS (Ground). D TESTCKOCT, TESTCKOCT90, TESTCKBIT and TESTCKBIT90 connected to VCC. RXRSVITACT register = 0X87 7.1.4. Using the Reed Solomon Decoder only IEXT(2:0) QEXT(1:0) TESTIERA REED SOLOMON DECODER TESTQERA TESTCKOCT TESTCKOCT90 TESTSYNC The Reed-Solomon decoder input data stream is made of 8-bit parallel data coming on (from MSB to LSB): IEXT(2:0), QEXT(2:0), TESTIERA and TESTQERA pins. The data stream is clocked on TESTCKOCT rising edge; there is a Pi/2 phase delay between TESTCKOCT and TESTCKOCT90 clocks. The TESTSYNC signal must be supplied to mark each sync byte occurence. 7.2. Setting the Sync and Sync Loss Criterions We address here the programming of the RXSYNCWCTL and RXDESYNCWCTL registers. The most important function for the evaluation of data from the MPEG-2 Transport Stream (TS) is the sync 30 Rev. D - April 1999 TSS902E acquisition. The actual synchronization of the TS depends on the number of correct sync bytes necessary for the device to synchronize and on the number of distorded sync bytes which the device can not cope with. Five consecutive correct sync bytes are usually considered as sufficient for sync acquisition and two or more consecutive corrupted sync bytes should indicate sync loss. D RXSYNCWCTL - SY[2:0] = 5 D RXDESYNCWCTL - DSY[2:0] = 2 Mismatching bits are allowed during the sync bytes search; you can define the maximum allowed number of mismatching bits when comparing the data stream to the expected sync byte. Let us take an example: the expected sync byte is 0x47; if you allow one mismatching bit, then the following bytes will be considered as valid sync bytes: 0x46, 0x45, 0x43, 0x4F, 0x57, 0x67, 0x07 and 0x97. Although you can set the number of mismatching bits to 0, 1 or 2, it is recommended to set it to zero so that the device does not get synced on wrong data. D RXSYNCWCTL - MSY[1:0] = 0 Once the Frame sync is got, the device may loose it whenever the expected sync byte can not be found. A mismatching bits mechanism also exists for sync loss conditions. Let us suppose that we expect a 0x47 value as sync byte. If the device reads 0x46, it will consider it as a valid sync byte if you have set the number of allowed mismatching bits to one. In that case, the device will remain synced. A value of one is a good trade-off for sync loss conditions. D RXDESYNCWCTL - MDS[1:0] = 1 A time out value may be defined to program the maximum duration of the sync word search after the bit sync is found. Once the time out duration is elapsed, an interrupt is generated and the bit sync state machine goes one step beyond. The interrupt may be used by the external system to change the BER threshold, for example. This parameter is not significant for the device to synchronize properly. D RXSYNCWCTL - TOV[1:0] = 0 We can now summarize these registers setup with: D RXSYNCWCTL = 0x05 D RXDESYNCWCTL = 0x0A Rev. D - April 1999 31 TSS902E 8. AC Characteristics 8.1. Reset Timing PARAMETER / EVENT TRSTLRSTH RESETB minimum pulse width DEFINITION MIN 10 MAX UNITS usec The Resetb signal is asynchronous. 8.2. Microprocessor Write Timing PARAMETER / EVENT TADVASL TASLADX TCSLCSH TWLWH TDVWH TWHDX Address setup to AS low Address hold from AS low DEFINITION MIN 5 5 20 20 10 MAX UNITS nsec nsec nsec nsec nsec nsec Chip Select minimum pulse width Write signal minimum pulse width Data setup to end of write (CS high or RDWRB high) Data hold from end of write (CS high or RDWRB high) The device internal write condition is: CS low and RDWRB low. 32 Rev. D - April 1999 TSS902E 8.3. Microprocessor Read Timing PARAMETER / EVENT TADVASL TASLADX TCSLCSH TRHRL TRHDV TCSHDX TRLDZ Address setup to AS low Address hold from AS low DEFINITION MIN 5 5 20 20 MAX UNITS nsec nsec nsec nsec Chip Select minimum pulse width Read signal minimum pulse width Read start to output valid End of read to invalid output End of read to high impedance 40 nsec nsec nsec The device internal read condition is: CS low and RDWRB high. 8.4. Microprocessor data bus interface In systems in which the TSS902E DUP data bus is shared with others devices, it is mandatory to isolate the TSS902E DUP bus by inserting an octal bidirectional buffer between the device DUP bus and the external system microcontroller data bus, as shown in the following figure: CS RDWRB TSS902E System Data Bus DUP (7:0) CS RDWRB Rev. D - April 1999 33 TSS902E 8.5. Interrupt Timing After IRQ output goes down, the microcontroller starts the interrupt registers read operation (RxVitRSInt0 & RxVitRSInt1) in order to find the interrupt origin. Both registers contents must be read and stored; reading these registers clears them. As long as these registers remain uncleared, the IRQ signal stays at low level. A CS rising edge transition indicates an end of read. Two CKBITOUT rising edges after end of read, the IRQ signal returns to high level. The microcontroller must guarantee 4 clock periods between two interrupt registers reading. 8.6. IEXT[2:0] and QEXT[2:0] Inputs Timing PARAMETER / EVENT TIQVCKLH TCKLHIQX DEFINITION IEXT & QEXT setup to CKBITEXT high IEXT & QEXT hold from CKBITEXT high MIN 5 5 MAX UNITS nsec nsec 8.7. Outputs Timing PARAMETER / EVENT TCKDATA TCKSYNCOUT TCKFRAMEOUT TCKBURSTOUT TCKDATAS DEFINITION Delay from CKOCTOUT clock falling edge to DATAOUT. Delay from CKOCTOUT clock falling edge to SYNCOUT. Delay from CKOCTOUT clock falling edge to FRAMEOUT. Delay from CKOCTOUT clock falling edge to BURSTSYNCOUT. Delay from CKBITOUT clock falling edge to DATAOUTS. MIN 5 5 5 5 5 MAX UNITS nsec nsec 34 Rev. D - April 1999 TSS902E 8.8. PLL block PLL block functionality requirements: G Enable the PLL block by setting the RxRSVitAct register PLLE bit. G The RxVitFreqIn register FREQ[6:0] and VCOC bits must be set as explained in the Registers section. G The code rate must be defined through the RxVitRate register and the manual mode must be selected through the RxVitControl one. The above timing diagram requires FREQ[6:0] to be set to 00H and VCOC to 0; the code rate is 3/4 (RxVitRate = 04H). The internally generated depuncturing clock can be observed at the CKBITOUT pin. Rev. D - April 1999 35 TSS902E 8.9. Depuncturing block PARAMETER / EVENT TCKBERSIQH TCKBERSIQL TCKBDOUTV TCKBCKOUT DEFINITION Delay from TESTCKBIT clock falling edge to erasei/eraseq rising edge. Delay from TESTCKBIT clock falling edge to erasei/eraseq falling edge. Delay from TESTCKBIT clock falling edge to depunctured output data valid. Delay from TESTCKBIT clock falling edge to CKBITOUT falling edge. MIN MAX 20 20 20 UNITS nsec nsec nsec nsec Depuncturing block test requirements: G Enable the Depuncturing block by setting the RxRSVitAct register DPE bit. G The code rate must be defined through the RxVitRate register and the manual mode must be selected through the RxVitControl one. If the code rate is different to 1/2 the Synchro-bit must be enable (set SYBE) G The TESTCKBIT clock frequency and phase must be set properly, according to the selected code rate. In the above timing diagram the depuncturing rate is 3/4 (RxVitRate = 04H). 36 Rev. D - April 1999 TSS902E The above timing diagram shows a Depuncturing block test sequence using a 7/8 rate. Rev. D - April 1999 37 TSS902E 8.10. Viterbi decoder Viterbi decoder test requirements: G Enable the Viterbi decoder by setting the RxRSVitAct register VE bit. In the above sequence, we assume that a 3/4 code rate is used; the incoming data is already depunctured and sequenced by the TESTCKBIT clock. G The TESTIERA and TESTQERA inputs must be controlled accordingly to the 3/4 rate. G In Viterbi test mode, the decoded bits can be found on DATAOUT(0) or DATAOUTS outputs after 290 TESTCKBIT clock periods (the Viterbi decoder latency). G The CKBITOUT output clock must be checked. An other possible Viterbi test sequence is to feed IEXT and QEXT with data of code rate 1/2 (no puncturing); in that case, the TESTIERA and TESTQERA inputs must be held low continuously. 38 Rev. D - April 1999 TSS902E 8.11. Synchro-Frame block Synchro-Frame block test requirements: G Enable the Synchro-Frame block by setting the RxRSVitAct register SYE bit. In the above timing diagram, the incoming data onto IEXT(2) is supposed to be the Viterbi decoder output, clocked by the TESTCKBIT signal. G The RxRSFrameL register is set to its default hexadecimal CC value (a 204 bytes frame length). G The RxSyncWord register is set to its default hexadecimal 47 value. G The output data can be read onto DATAOUT(7:0) on CKOCTOUT clock falling edge. G The SYNCOUT signal goes high whenever the sync word is found. G The BURSTSYNCOUT signal goes high and remains high as long as the sync word is found. Rev. D - April 1999 39 TSS902E 8.12. De-Interleaver block De-Interleaver block test requirements: G Enable the de-interleaver block by setting the RxRSVitAct register DIE bit. In the above timing diagram, the incoming data FromSyncFrame(7:0) is supposed to be the Synchro-Frame block output and must be valid on the TESTCKOCT clock falling edge. In test mode, FromSyncFrame(7:0) is made, from MSB to LSB of: IEXT(2:0), QEXT(2:0), TESTIERA and TESTQERA. G There is a Pi/2 delay between TESTCKOCT and TESTCKOCT90 clocks. G The RxRSFrameL register is set to its default hexadecimal CC value (a 204 bytes frame length). G The RxSyncWord register is set to its default hexadecimal 47 value. G The TESTSYNCIN input must be high whenever the sync byte is present onto the input bus. G If sync words periodically appear into the input data stream, the BURSTSYNCIN input must be kept high. G The output data can be read onto DATAOUT(7:0) on CKOCTOUT clock falling edge after the de-interleaver block latency (1280 TESTCKOCT clock periods). The output data may also be read onto the DATAOUTS serial output on CKBITOUT falling edge. 40 Rev. D - April 1999 TSS902E 8.13. Reed-Solomon decoder Reed-Solomon decoder test requirements: G Enable the Reed-Solomon block by setting the RxRSVitAct register RSE bit. In the above timing diagram, the incoming data FromDeInterleaver(7:0) is supposed to be the De-Interleaver block output and must be valid on the TESTCKOCT clock falling edge. In test mode, FromDeInterleaver(7:0) is made, from MSB to LSB of: IEXT(2:0), QEXT(2:0), TESTIERA and TESTQERA. G There is a Pi/2 delay between TESTCKOCT and TESTCKOCT90 clocks. G The RxRSFrameL register is set to its default hexadecimal CC value (a 204 bytes frame length). G The RxSyncWord register is set to its default hexadecimal 47 value. G The TESTSYNCIN input must be high whenever the sync byte is present onto the input bus. G If sync words periodically appear into the input data stream, the BURSTSYNCIN input must be kept high. G The output data can be read onto DATAOUT(7:0) on CKOCTOUT clock falling edge after the Reed-Solomon decoder latency (2 x FrameLength + 50bytes). Rev. D - April 1999 41 TSS902E 8.14. Descrambler block Descrambler block test requirements: G Enable the Descrambler block by setting the RxRSVitAct register EDE bit. In the above timing diagram, the incoming data FromReedSolomon(7:0) is supposed to be the Reed-Solomon decoder output and must be valid on the TESTCKOCT clock falling edge. In test mode, FromReedSolomon(7:0) is made, from MSB to LSB of: IEXT(2:0), QEXT(2:0), TESTIERA and TESTQERA. G There is a Pi/2 delay between TESTCKOCT and TESTCKOCT90 clocks. G The RxRSFrameL register is set to its default hexadecimal CC value (a 204 bytes frame length). G The RxSyncWord register is set to its default hexadecimal 47 value. G The TESTSYNCIN input must be high whenever the sync byte or its complemented value are present onto the input bus. G If sync words periodically appear into the input data stream, the BURSTSYNCIN input must be kept high. G The output data can be read onto DATAOUT(7:0) on CKOCTOUT clock falling edge after the Descrambler block latency (half a TESTCKOCT period). G The BURSTSYNCOUT signal goes high on B8H occurence and remains high for a 188 bytes duration. 42 Rev. D - April 1999 TSS902E 9. Absolute Maximum Rating and Operating Conditions 9.1. Absolute Maximum Rating Table 6: Absolute Maximum Ratings D D D D Storage Temperature . . . . . . . . . . . . . . . . . . . . Voltage on any other Pin to VSS . . . . . . . . . . . IOL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . -65 to +150C -0.5 to +6.5 V 3W 9.2. Operating Conditions Table 7: Operating Conditions D Ambient Temperature Under Bias Space .............................. Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D VDD High Speed versions . . . . . . . . . . . . . . . . . . . . . -55 to +125C -55 to +125C 4.5 to 5.5 V Note: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Rev. D - April 1999 43 TSS902E 10. DC Characteristics - Space and Military Ranges Table 8: DC Characteristics at 5V +10%, TA= -55 to +125C Symbol VIL VIH VOL VOH IIL Parameter Input Low Voltage Input high Voltage Output Low Voltage Output high Voltage Input Leakage Current No pull-up/pull-down With pull-up With pull-down 3-State Output Leakage Current Operating Current Viterbi block Reed-Solomon block Standby Current Min -0.5 0.2VDD + 0.9 Typical Max 0.2VDD - 0.1 VDD + 0.5 0.4 0.4 Units V V V V Test Conditions IOL= 3 mA IOL= 6 mA IOH= -10 A 2.4 +/- 5 -50 +360 +/- 1 20.5 2.2 20 +/- 5 A A mA/MHz mA IOZ ICCOP ICCSB 44 Rev. D - April 1999 TSS902E Package mm inch Figure 2: 132 pins MQFPF Rev. D - April 1999 45 TSS902E Ordering Information TS S 902E S A /883 Packaging A: MQFP Temperature Range 132 pins Product Line M: Military -55_C B: Die S: ASSP to +125_C Flow Part Number S: Space -55_C to -E: Engineering Sample 902 +125_C Blank: Standard Military /883: MIL 883 Compliant B or S E: Radiation P883: MIL 883 Compliant B+ Tolerant Z: PIND Test SB: SCC9000 Level B Depuncturing SC: SCC9000 Level C SL3: LAT3 and Viterbi deSL2: LAT2 Example: coder option SL1: LAT1 TSS902E Hxxx: Customer Code (without PLL) S A /883 (-E a @ Mil. Temperature) FRANC E yyww Lot Nb The information contained herein is subject to change without notice. No responsibility is assumed by Atmel Wireless & Microcontrollers for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use. 46 Rev. D - April 1999 |
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